1. Field of the Invention
The present invention relates to a dynamic bias control circuit for a digital-to-analog converter, and more particularly, to a dynamic bias control circuit utilizing a differential amplifier for dynamic adjustment.
2. Description of the Prior Art
Conventionally, a digital-to-analog converter of a 10/100 high-speed chip includes a plurality set of switching current sources. For example, twenty sets, forty sets, or sixty sets of switching current sources are coupled together in parallel. Referring to partial circuits of a conventional high-speed network chip, the high-speed network chip includes a digital-to-analog converter and a switching current source. With improvements in integrated circuit manufacturing, the supply voltage terminal VDD decreases. In 0.18 μm manufacturing, the supply voltage terminal VDD can be assumed to be 1.8V. In this situation, the value of the first output voltage terminal Vout1 will fall between (VDD−1.25) and (VDD+1.25), where there is only a difference of 550 mV between the ground and the lowest voltage, and which results in compressing the switching current source below entering the triode region. As a result, the current provided by the current source becomes smaller and the amplitude of output signals descends. As the supply voltage terminal VDD becomes lower, the above mentioned phenomenon becomes more serious.
In order to solve the above-mentioned problem, areas of current cells are increased to lower their saturation drain voltage (Vdsat) so that it is more difficult for the current cells to enter the triode region. Nevertheless, it is not beneficial in cost if the element areas of tens of switching current source are increased simultaneously.